So I’ve asked a question and hopefully you made it through it, possibly with a little help. Now, depending on experience, I’ll ask if you’ve worked in either Quartus or Vivado to develop constraints for the circuits. This helps fill me in how much of the flow you’ve worked on. So lets discuss constraining the synchronizer.
How would you constrain the synchronizer in Quartus or Vivado?Answer
The design half of the synchronizer is done, but now how do we constrain the tools for the best results. Years ago, we would simply set_false_path between the two clocks. Then clock groups were added. These worked fine for older technologies where clock speeds were relatively low. However, now even FPGAs can get up to >500Mhz in some cases.
In order to reduce the MTBF of the synchronizer, the RX_CLOCK FFs should be placed near to each other. From experience, both Quartus and Vivado pack back to back FFs pretty tightly and in general no extra constraints are needed. Xilinx offers Metastability hardened FFs in the Ultrascale and Ultrascale+ or a constraint on synchronizers can be applied: (*async_reg = “true”*)
In Xilinx, I’ve also applied a set_max_delay between the RX and TX clock domains:
set_max_delay -datapath_only -from [get_clocks TX_CLOCK] -to [get_clocks RX_CLOCK] [expr min([join [get_property PERIOD [get_clocks “TX_CLOCK RX_CLOCK”]] ,])]
Unfortunately, Altera doesn’t offer the datapath_only switch, although a similar max delay could be set, it would just be a little tighter.
Since not everyone has worked all aspects of the flow I consider this knowledge less critical than actually how to implement the synchronizer. It’s just nice to know and a plus for me that someone has worked on more of the flow.