SV Blog SystemVerilog Blog
Related Articles
The next question is more general. Just basically to get an idea if you know the parts of a FIFO and how they work together. I would recommend reading Cliff Cummings paper on the subject: http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf
This is a short post, since Cliff covered this very thoroughly and there is no reason for me to add much. Key take aways:
Grey coding
Full/ empty generation and why they are pessimistic such that you won’t ever overflow or underflow the FIFO.
for 10g Ethernet TX path, it’s running at 156Mhz. I got a parser runs much higher frequency, etc. 500Mhz plus. Apparently I need an async ingress FIFO to be put between the TX path and a design. But FIFO will introduces latencies. Is there a better way, that can send bursty packets cross domain without using such FIFOs? I imagine HFT industry might use some solutions to cross domain without introducing extra latencies?
The problem on the TX side is that you cannot starve the MAC when you are sending data, so you will need a FIFO or guarantee that you can keep the MAC fed. There are more efficient ways than using a vendor FIFO. I came up with one that I use, but I keep confidential. Nvidia has a patent on a 0 delay CDC FIFO, but I don’t think it’s practical for an FPGA.