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SV Basics: Basic Types

Shortly I’m going to be starting up a project that I hope people will support with views, shares and contributions. Hopefully this will be a learning experience for all, including myself. To begin I would like to go over some SystemVerilog basics.

When Verilog was introduced, there were only a few data types:

reg – conveys the concept of a storage element. This however isn’t really true. a reg type is simply something assigned by an always block.

wire – anything assigned by an assign statement. This can strictly be a wire or combinational logic.

reg types are obsolete and shouldn’t be used in new designs. Wires are still required for tri-state drivers:

assign pci_data = pci_en ? pci_out : ‘z; // ‘z to be discussed shortly.

Verilog has a feature where it will infer single bit wires if not defined. Coding this way is a bad practice. One way to avoid this is to encapsulate a module file as follows:

`default_nettype none

module test () …


`default_nettype wire

SystemVerilog Types:

SystemVerilog implements two new types:

logic – 4 state values for simulation : 0, 1, X, Z

bit – two state 0, 1. Can speed up simulations, but not modeling X can cause problems.

It’s recommended that logic types be used for all except tri state signals where wires should be used.

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