Home / FPGA / SV Intro #1: Hello World

SV Intro #1: Hello World

Introduction

I have always loved digital design. When I was kid, I spent all my waking hours working on my Apple ][+. I knew what I wanted to do when I went to college and luckily I landed a job designing ASICs. I was also a bit cocky and wanted to write a book. I partnered with a colleague at the time and we were going to write a book on VHDL.

Then I lost the desire. He wanted to write the book as though VHDL was a programming language. HDLs are not programming languages and I think that high level programmers wouldn’t make good digital design engineers and good digital design engineers would make poor high level programmers. I have known some who can cross between, but they are few and far between.

Now 25+ years later, we have affordable FPGA platforms that enthusiasts can program at home. Now I think the “Hello World” example is valid and I’m going to use it. The goal of my project is multi-pronged. I want to get you running using efficient SV. I want to teach design trade offs for low power and performance. I want us all to have fun along the way.

What you need to follow along

Hardware

I will be using a Zynq ULtrascale+ MPSOC board. (Altera: I’d be happy to do a Stratix 10, Arria 10 SOC or Cyclone 10 version in parallel if you’d like to donate one.)

I am hoping that the majority of the design can easily fit in a Zynq 7020, possibly a smaller one. I will be working in a 7020 and 7045 in parallel, possibly a Cyclone V SOC.

Operating System

I’m running on Ubuntu 16.04. For SOC software you will need a linux version, but we’ll cross that bridge many posts from now. For the FPGA work, you can use Windows, but I wouldn’t recommend it. The vast majority of professional FPGA engineers use Linux (Ubuntu, Centos or OpenSUSE). You can use a virtual machine.

Software

I will be using both Verilator and Tachyon-DA OSS_CVC at least until one proves incapable of doing what I want.

For wave viewing I’ll be using Dinotrace and GTKwave, again until one proves the better.

Verilator: https://www.veripool.org/projects/verilator/wiki/Installing

CVC: http://www.tachyon-da.com/

DinoTrace: https://www.veripool.org/wiki/dinotrace

GTKWave: http://gtkwave.sourceforge.net/

Hello World

SystemVerilog code

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// Simple hello world in SystemVerilog
module hello_world;
initial begin
$display("Hello World\n");
$finish;
end
endmodule // hello_world

OSS CVC

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fbmsi:~/projects/book> cvc64 hello_world.sv
OSS_CVC_7.00b-x86_64-rhel6x of 07/07/14 (Linux-elf).
Copyright (c) 1991-2014 Tachyon Design Automation Corp.
All Rights reserved. Licensed software subject to prohibitions and
restrictions. See OSS CVC artistic license included with release.
Today is Sat Aug 5 16:51:29 2017.
Elaborating source file "hello_world.sv"
Highest level modules:
hello_world
Compiling module 1 of 1.
CVC compilation 0.1 seconds elapsed.

EXECUTABLE SAVED TO 'cvcsim'.

End of OSS_CVC_7.00b-x86_64-rhel6x at Sat Aug 5 16:51:29 2017 (elapsed 0.1 seconds).

fbmsi:~/projects/book> ./cvcsim
OSS_CVC_7.00b-x86_64-rhel6x of 07/07/14 (Linux-elf).
Copyright (c) 1991-2014 Tachyon Design Automation Corp.
All Rights reserved. Licensed software subject to prohibitions and
restrictions. See OSS CVC artistic license included with release.
Today is Sat Aug 5 16:54:15 2017.
Highest level modules:
hello_world

Hello World

Halted at location **hello_world.sv(6) time 0 from call to $finish.

Verilator

For Verilator, we need a top level C++ program:

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#include "Vhello_world.h"
#include "verilated.h"
int main(int argc, char **argv, char **env) {
Verilated::commandArgs(argc, argv);
Vhello_world* top = new Vhello_world;
while (!Verilated::gotFinish()) { top->eval(); }
delete top;
exit(0);
}
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fbmsi:~/projects/book> verilator -Wall -cc hello_world.sv -exe sim_main.cpp
fbmsi:~/projects/book> cd obj_dir/
fbmsi:~/projects/book/obj_dir> make -j -f Vhello_world.mk
g++ -I. -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=0 -Wno-char-subscripts -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -c -o sim_main.o ../sim_main.cpp
g++ -I. -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=0 -Wno-char-subscripts -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -c -o verilated.o /usr/local/share/verilator/include/verilated.cpp
/usr/bin/perl /usr/local/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vhello_world.cpp > Vhello_world__ALLcls.cpp
/usr/bin/perl /usr/local/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vhello_world__Syms.cpp > Vhello_world__ALLsup.cpp
g++ -I. -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=0 -Wno-char-subscripts -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -c -o Vhello_world__ALLsup.o Vhello_world__ALLsup.cpp
g++ -I. -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=0 -Wno-char-subscripts -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -c -o Vhello_world__ALLcls.o Vhello_world__ALLcls.cpp
Archiving Vhello_world__ALL.a ...
ar r Vhello_world__ALL.a Vhello_world__ALLcls.o Vhello_world__ALLsup.o
ar: creating Vhello_world__ALL.a
ranlib Vhello_world__ALL.a
g++ sim_main.o verilated.o Vhello_world__ALL.a -o Vhello_world -lm -lstdc++ 2>&1 | c++filt
fbmsi:~/projects/book/obj_dir> cd ..
fbmsi:~/projects/book> obj_dir/Vhello_world
Hello World

- hello_world.sv:6: Verilog $finish

Result:

Congratulations! You have created and executed your first Systemverilog program. It doesn’t seem like much now, but when it’s done, I hope you’ll agree that it was worthwhile.

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