Tag Archives: fpga

Earlier I had posted my simple hello_world.sv example. Now I want to dive into a slightly more comprehensive example. This example also communicates to the testbench so I can begin to explore SystemC for testing. hello_world.sv 123456789101112131415161718192021222324252627282930313233`timescale 1 ns / 10 ps module hello_world   #   (    parameter …

One of my thoughts was to use an even-odd approach. This is typically done when using GPUs in a sequential fashion. I decided to do this pipelined. This approach turned out to be extremely inefficient in retrospect. In a future post, I’ll do a state machine based approach which will …

The first approach I attempted was a completely parallel approach as shown in the diagram below: The advantage to this approach, if it meets timing, is that it will produce a result every clock cycle, it’s compact, easy to understand, and uses a reasonable amount of logic. compare.sv 123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197module compare …

I had Been trying to come up with a good problem to illustrate design trade offs when I came across this: Design a module that can sort four numbers. I’ve only done a few sorts in BASIC ages ago and more recently in OpenCL. Off the top of my head, …

Introduction I have always loved digital design. When I was kid, I spent all my waking hours working on my Apple ][+. I knew what I wanted to do when I went to college and luckily I landed a job designing ASICs. I was also a bit cocky and wanted …