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Verilator Setup

Recently I posted regarding my introduction to SystemVerilog. In it I laid out my case for using either CVC or Verilator. As was pointed out, there are other solutions, some of which I covered in previous posts. Where the introduction is going and ultimately where my project is going will take it beyond the capabilities of EDA playground and likely vendor tools if they are instance limited.

I decided to go whole hog into Verilator and spent the better part of today learning enough SystemC to write a simple testbench. First I’d like to give Kudos to Forte Design Systems (now part of Cadence). They have a series of videos that were invaluable for getting me started:

Forte Design Systems Videos

In my next post, I’m going to go over the problem I was solving as it will point out design trade offs and how to approach a problem. The problem I’m going to tackle is how to sort Numbers in a hardware design. This might sound simple, but there are many ways to do it, and there are trade-offs for them, which I will go over.

For now, here is my Verilator project.

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