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Tag Archives: systemverilog

Hello World Revisited

Earlier I had posted my simple hello_world.sv example. Now I want to dive into a slightly more comprehensive example. This example also communicates to the testbench so I can begin to explore SystemC for testing. hello_world.sv 123456789101112131415161718192021222324252627282930313233`timescale 1 ns / 10 ps module hello_world   #   (    parameter …

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SV Intro #1: Hello World

Introduction I have always loved digital design. When I was kid, I spent all my waking hours working on my Apple ][+. I knew what I wanted to do when I went to college and luckily I landed a job designing ASICs. I was also a bit cocky and wanted …

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